Trench isolation techniques have been considered as alternatives to local oxidation of silicon (LOCOS) isolation techniques because trench isolation techniques provide fully recessed oxides, may be planarized, do not result in the formation of bird's beaks oxide extensions and typically do not suffer from field oxide thinning effects. Such trench isolation techniques are more fully described in U.S. Pat. No. 5,750,433 to Jo entitled "Methods of Forming Electrically Isolated Active Region Pedestals Using Trench-Based Isolation Techniques", U.S. Pat. No. 5,753,562 to Kim entitled "Methods of Forming Semiconductor Devices In Substrates Having Inverted-Trench Isolation Regions Therein", and U.S. Pat. No. 5,858,842 to Park entitled "Methods of Forming Combined Trench and Locos-Based Electrical Isolation Regions In Semiconductor Substrates, all assigned to the present assignee, the disclosures of which are hereby incorporated herein by reference.
Unfortunately, the performance of thermal oxidation steps when forming trench isolation regions may cause volume expansion defects and dislocations to form adjacent the sidewalls and corners of the trenches as migrating oxygen reacts with the silicon at the trench sidewall interfaces. As will be understood by those skilled in the art, these defects and dislocations can degrade the electrical characteristics of devices formed in active regions which extend adjacent the trench isolation regions.
To address these limitations associated with conventional trench isolation techniques, attempts have been made to add stress-relieving liners (e.g., ON and ONO liners) to the sidewalls and bottoms of trenches. Such attempts are disclosed in U.S. Pat. Nos. 4,631,803, 5,189,501, 5,190,889 and 5,206,182. Unfortunately, conventional processing techniques may cause removal of the stress relieving lining material and result in the formation of voids which can degrade the electrical isolation characteristics of the trench isolation regions. For example, as illustrated by FIGS. 1A-1B, conventional processing techniques may cause a trench nitride layer 10 to become recessed and the formation of a void as illustrated by highlighted region 14.
In particular, FIG. 1A illustrates a trench isolation region at an intermediate stage of processing. This trench isolation region may be formed by thermally oxidizing a face of a substrate 1 to define a pad oxide layer 2 and then depositing a silicon nitride masking layer 4 on the pad oxide layer 2. The silicon nitride masking layer 4 may then be patterned using conventional photolithographically defined etching steps. The silicon nitride masking layer 4 may then be used as an etching mask during the formation of a trench 6 in the substrate 1. The sidewalls and bottom of the trench 6 may then be thermally oxidized to define a trench oxide layer 8. A trench nitride layer 10 may then be deposited on the trench oxide layer 8 and on the silicon nitride masking layer 4. The trench may then be filled with an electrically insulating material 12 (e.g., USG). A planarization step may then be performed, using the silicon nitride masking layer 4 as a planarization-stop. Then, as illustrated by FIG. 1B, an etching step can be performed using a wet etchant (e.g., phosphoric acid) to remove the silicon nitride masking layer 4. Unfortunately, this etching step may also cause the trench nitride layer 10 to become recessed, as illustrated. The extent of this recession may be reduced by using thinner trench nitride layers 10, however, the use of thinner trench nitride layers 10 may reduce the stress-relieving benefits provided by the trench nitride layers 10. Such techniques to use thinner trench nitride layers 10 are more fully disclosed in U.S. Pat. No. 5,447,884.
Thus, notwithstanding the above-described methods of forming trench isolation regions, there continues to be a need for improved methods of forming trench isolation regions.